19 years ago Intel introduced the concept of buil-ding-in reliability. It basically means to control design, processes and materials which are used for producing chips rather than testing the chip itself.

This concept is also very well suited to secure the reliability of power electronics systems. Today “zero defect” throughout the supply chain is a requirement. Everything has to be done right from the beginning, starting with the require-ments concerning reliability and mission profile.

After having worked out a first design the next step in the design process is “Virtual perfor-mance assessment” which includes electrical, thermal and EMI simulations. The results are compared with data sheets and standards. The fourth step is “Reliability assessment” based on the “physics of failure”, and physical models for Life-time prediction. The fifth step is “Robustness validation “, a brand new validation philosophy for components and modules/ ECUs, which has been worked out by many automotive industries under the umbrella of ZVEI, SAE, JSAE. The handbook J 1879 is available since 04/2007, and J1211 will be published 04/2008.

Prof. Eckhard Wolfgang (ECPE) will chair the workshop together with Michel Mermet-Guyennet, (PEARL) and Thomas Harder (ECPE).

All presentations and discussions will be in English.