This tutorial will teach the various effects of parasitic inductance (LS) in power electronics. As power density and current density is continuously growing, parasitic inductance and resistance become limiting factors, more and more. The use of unipolar devices, e.g. WBG-devices, requires minimum parasitic inductance to allow fast switching. The figure of merit is the product of parasitic inductance times rated current (LS*Inom) which is increasing with current density, if designs do not improve.

Not only overvoltage during turn-off is the problem but for bipolar power semiconductors like IGBTs and freewheeling diodes, parasitic inductance causes disadvantageous current waveforms.

In systems, which have snubber capacitors additional to the DC-link capacitor and parasitic inductance in between, oscillations between these capacitors occur.
When considering power semiconductors, in parallel, current sharing of voltage-controlled devices like IGBT, MOSFET and JFET can be affected by the presence of even very small parasitic inductance.

Parasitic inductance within the control circuit (gate circuit) decouples driver and Gates of the devices, leading to increased short circuit current, for example.

To introduce these topics the tutorial will start with the basics of switching inductive loads and discussion of related waveforms. Investigations on the different effects, will follow. The discussion of paralleling will be accompanied by case studies. Geometries of conductors and system design for low parasitic inductance and good current sharing will be another main part and the conclusions will summarize the benefits of related system design – clean switching and low losses.

All presentations and discussions will be in English.