Registration Deadline: 11 November 2020
This tutorial will teach the various effects of parasitic inductance (LS) in power electronics. As power density and current density is continuously rising, parasitic inductance and resistance become more and more the limiting factors. The problem is the product inductance times current (LS*I) rising, simultaneously, if designs do not improve.
Not only overvoltage during switching is the problem but for bipolar power semiconductors like IGBTs and freewheeling diodes, parasitic inductance causes disadvantageous current waveforms.
In systems which have snubber capacitors additional to the DC-link capacitor and parasitic inductance in between, oscillations between these capacitors occur.
When considering power semiconductors in parallel the current sharing of controlled devices like IGBT, MOSFET and JFET can be affected by the presence of small parasitic inductance.
Parasitic inductance in the control circuit (gate circuit) decouples driver and the gates of the devices leading to increased short circuit current, for example.
To introduce these topics the tutorial will start with the basics of switching inductive loads and discussion of related waveforms. Investigations on the different effects will follow. The discussion of paralleling will be accom-panied by case studies. Geometries of conductors and system design for low parasitic inductance and good current sharing will be another main part and the conclusions will summarize the benefits of related system design – clean switching and low losses.
All presentations and discussions will be in English language.